Advances in system chip technology and integration has allowed chips to operate at increasingly higher frequencies. For many systems we find that some of the most critical paths in the system are not on-chip, but between chips. For example the next generation of IBM systems being designed could operate at faster than 4.7 ns. per cycle; but, with the current design for the next generation of chips having physical locations of a multi-chip module (MCM) and memory cards on the same board a delay across the longest nets from say the MCM to a memory card takes a minimum of 5.3 ns. This means that the system can not work at a 5.0 ns cycle time unless other methods are found. Therefore, there is a need to improve on the methods for increasing and maintaining the desired high frequencies of intrachip communication in these future systems, and yet until this invention, the prior attempts fell short.